Research On FPGA High Speed And Large Capacity External Packet Buffer Technology

As a new type of network technology,Software Defined Network(SDN)separates the control functions of the traditional switching/routing equipment from the system,thereby facilitating the network to become more flexible,having a better scalability,and facilitating the support of new network technologies and business innovation.The SDN data forwarding system architecture serves as a storage and forwarding subsystem of the SDN switch.First,the received data stream is identified and processed,and then an enqueue cache operation is performed according to the processing result.The 100 G high-speed interface of the SDN data forwarding system requires the use of high-speed and large-capacity external cache,which is also the key technology studied in this paper.Based on the research topic “Study of software-defined network data forwarding system architecture and key technologies” undertaken by the laboratory,this article conducts indepth research on queues and message caching mechanisms.The thesis first introduces the background of the research,summarizes the existing message caching mechanism,summarizes the key points of the queue and message caching technology,introduces the overall design of the SDN data forwarding system and the hardware implementation plan,and studies in detail The operating performance of the existing plug-in memory.Next,a hierarchical wire-speed cache architecture composed of SRAM and SDRAM memory is proposed,in which the external SDRAM is used as a cache entity to provide large-capacity data frame storage,multi-channel parallel technology is used for read and write,and SRAM is responsible for storing each queue.Head and tail data.Third,the overall design of the multi-channel hierarchical wire-speed cache architecture and the detailed design of each submodule are described.Fourth,the key modules in the multi-channel hierarchical wire-speed cache architecture are simulated and verified.Finally,the above-mentioned cache architecture is verified at the board level.The verification result shows that the architecture can realize fast and low-latency switching.