Research On Verification Method Of FPGA Logic Circuit Based On High Frequency Signal Measurement

With the rapid development of integrated circuits,whether in the field of highly integrated ASIC or FPGA without production line mode,verification has occupied an increasingly important position in the entire chip development process,and at the same time,the efficiency of the IC industry for verification is high.And completeness also put forward higher requirements.The continuous development of verification languages has driven the continuous improvement of verification methods.The System Verilog-based UVM verification methodology has become one of the most advanced and most efficient verification methods today due to its high level of abstraction,constrained random excitation,and reusability of the verification platform.The focus of this dissertation is to analyze the high-frequency signal measurement in the internship project to solve all the functional points of the FPGA logic circuit and build a UVM verification platform based on function coverage and random constraint excitation for functional verification.The functions that the circuit needs to verify mainly include the PCI register interface module correctly configuring the corresponding offset address register on the chip to control and monitor the working status of the system;the SPI interface module correctly responds to the read and write requests issued by the PCI register interface,generates clocks,and transmits data and other SPI bus timings.The signal accesses the external register space;the FFT arithmetic operation module completes the operation mode and parameter configuration according to the register control,and the arithmetic unit of the internal fast Fourier transform module,inverse trigonometric function module,etc.correctly solves the received real part and imaginary part data,Finish the information extraction of the original signal;RX_JESD204B interface module receives the high-speed 4-channel differential signal that the external AD device sends correctly and finishes the digital system conversion.In order to ensure the completeness and correctness of the verification,the corresponding verification strategy is formulated in this paper,including the UVM verification platform architecture planning,functional coverage orientation,and RGM register solutions.At the same time,many key mechanisms of UVM are used to ensure the reusability and good expandability of the verification platform,including the virtual sequence mechanism,the factory mechanism,the config_db mechanism,and the callback mechanism.After completing the establishment of the UVM verification platform,18 test cases were developed based on the extracted twelve functional points,58 assertions of various types were set up,and five types of coverage group settings were completed.Validate the simulation using scripts during simulation to analyze the log file verification results.By modifying the weights of incentives and constraints and adding random seeds,the index of 100% coverage of functions was finally achieved.The code coverage and assertion coverage also met the project requirements.By using the UVM verification methodology,the functional verification of the DUT circuit has been completed efficiently,which not only shortens the project cycle,but also builds a reusable verification platform to lay the foundation for related verification work in the future.