Investigation On Simulation Of 3D NAND Flash Structure And Programming/Erasing Characteristic

With the development of social information,people put forward higher requirements for information storage capacity,read and write speed and power consumption.Therefore,the miniaturization of memory devices has gradually become a research hotspot,but the decrease of device size will lead to the decrease of device reliability,thus limiting the development of memory miniaturization.However,the new memory,which uses the three-dimensional structure instead of the traditional planar structure,increases the space utilization of the device.Changes in 2D to 3D storage have led to dramatic increases in memory capacity,significantly speeding up programming and writing times and significantly lower power consumption,all of which have given 3D NAND Flash top priority to researchers and industry.In this paper,three aspects of capacitance model calculation,device electrical characteristics simulation and threedimensional memory preparation process simulation are studied.The influence of device size on the device writing and erasing characteristics is studied.Firstly,according to the capacitive coupling theory and the structure of 3D double-gate and gate-all-around memory cell devices,a corresponding gate capacitance model is established,and the influence of gate dielectric thickness and gate spacing on the device gate capacitance is investigated.The simulation results show that there is a positive correlation between the coupling capacitance of double-gate and gate-all-around devices and gate dielectric thickness,and the device spacing has a negative correlation.Considering the influence of the coupling capacitance between memory cells in a 3 × 3 memory array by using the capacitance model.It is found that the increase of the device spacing and the reduction of the thickness of the gate dielectric both help to reduce the coupling capacitance between the memory cells,thereby reducing the self-capacitance Boost effect,thereby improving the erase reliability of the memory cell.Using Silvaco TCAD device simulation software,a 3D NAND Flash double-gate and gatering memory cell structure model is established.By using the FN tunneling mechanism,the transfer characteristic curves of memory cells under different device structure parameters can be obtained,and the programming / erasing operation is floated Gate charge curve.The results show that the device size variation has little effect on the storage characteristics of the ring-gate device and has higher reliability.Based on this,a multi-layer and multi-cell 3D dual-gate and gate-all-around device memory array model is established.By comparing the transfer characteristic curve and the floating gate charge curve under the same conditions,it is found that in the multi-layer multi-cell in the structure,the double-gate device is more disturbed by the coupling capacitor,while the reliability of the gate-all-around device is still higher than that of the double-gate device.Using the SEMulator 3D process simulation software,through the means of process simulation,a multi-layer structure model of the storage part of a 3D structure is constructed.By controlling the process conditions for the preparation of different sizes of device combinations,research device capacitance trends.The results show that there is a positive correlation between device capacitance and number of unit groups and gate-all-around thickness.