Asymptotically Linear Analysis And Gate Error Probability Allocation Schemes In Probabilistic Circuit

With the feature size of CMOS technology shrinking rapidly into the deep submicron,power density becomes higher and circuit's reliability is seriously influenced by thermal noise.For reducing power dissipation,decreasing supply voltage is a promising way.However,soft errors and the decreased supply voltage make circuits behave probabilistic,not deterministic.Therefore,the reliability evaluation of probabilistic CMOS circuits has become a critical part of this field,but the time-consuming nature of traditional methods has severely limited the research of probabilistic CMOS in other fields.Fortunately,some applications can tolerate a certain small error probability.That is to say,each gate error rate(ER)can be set a small value,nevertheless,the circuits can get 30% ~ 60% power savings since the power consumption decreases exponentially as logic gate error probability increases.Therefore,in the case of small error probability of the logic gate,this paper proposes to use Asymptotically Linear Analysis(ALA)to evaluate the reliability of the circuit.This method can overcome the time-consuming characteristic of the traditional method and the experimental results show that the time complexity is 3 to 4 orders of magnitude lower than BDEC algorithm.In this paper,another key challenge is to pledge to satisfy the limited output error probability in the presence of soft errors,thus,we provide three schemes,which are a)partly random allocation,b)power optimization based allocation,c)gate clustering allocation,for gate error probability assignment in logic and circuit design stage of VLSI design in this paper.During the power optimization,the approximately invariant switching activity in the asymptotically linear region makes the power model convex.Then,the optimization process can converge in a short period of time and achieve a considerable result.All the three criteria verified by conducting experiments on ISCAS'85 benchmark circuits and the simulation results demonstrate the feasibility of ALA and the performance of the proposed schemes.