Application Of Convolution Network Algorithm Based On Sdsoc

Convolution Neural Network(Convolutional Neural Network,CNN)is a branch of deep learning,the Network is especially good at the image recognition and parsing.It has a unique network structure,which can have better recognition results for mass image processing.The convolution neural network can effectively solve the problem of image deformation and displacement by means of weight sharing and subsampling.In view of its operational characteristics,the multiplicative and repetitive multiplication requires a great deal of computing resources and the support of large-scale bandwidth storage resources.In recent years,artificial intelligent ecosystem has been growing rapidly,which has become a hot spot for the search and design performance and efficiency of deep neural network.Therefore,this article which embarks from the convolution of the neural network model characteristics,combined with FPGA hardware advantage,from software algorithm and hardware resources to parallelism of analysis model,designs a kind of convolution network to accelerate the engine based on FPGA.First,in order to improve the processing speed of convolution network,this paper verifies a general acceleration scheme which maps convolution kernel cycle to actual circuit.Compared the calculation of the different structures,we maximize the speed calculation to improve computing data throughput,to reduce the invalid data handling bringing efficiency loss.Secondly we use the latest SDSoC optimizing compiler system which supporting C language development to improve the development cycle.Based on zedboard platform,a simple and efficient network model(lenet-5)were designed and implemented in this paper.In the test of MINST dataset,the acceleration effect is higher than that of the pure CPU platform.By using Vivado HLS high-level synthesis tool,new acceleration strategies are proposed to optimize the design of the accelerator IP core.We use Xilinx SDSoC to compare the performance impact of different data paths and to explore the optimization of data communication and data processing.The results show that by modularizing IP and overall architecture design,high data throughput and good parallelism can be used to achieve satisfactory results.