Research On The Data Reliability Of Network On Chip For Space Environment

With the reduction of chip feature size and the increase of system complexity,the system on chip integrating multiple processor cores has attracted more and more attention from developers.The application of scientific computing,image processing,military radar,meteorological observation and other applications continuously promote the development of high-density computing.While the traditional bus architecture on chip system because of poor scalability,low degree of parallelism of all sorts of reasons,has been a limiting factor in the development of multi-core system with high performance and high density computing.The presentation of network on chip effectively improves the performance of system on chip,with the characteristics of reusability,scalability,anticipatory and fault tolerance,making it become the main communication and interconnection structure in multi-core system.However,due to the interference of the space environment of various cosmic rays,and the earth's magnetic field,the reliability of inter core communication of aerospace devices is facing a serious threat,especially the transient fault seriously destroys the reliability of communication data and the stability of communication control.At any time,it may cause the system run error or even downtime.In the current target multi-core system,as the network on chip of the inter-core communication,there is no effective fault tolerance mechanism,threatened by transient failure,and it cannot meet the reliability requirements of the space environment.This thesis focuses on the data reliability of network on chip for space environment.The main work is as follows:Firstly,analyzing the relationship between calculation and communication of the target multi-core system,and the communication features of network and system.According to the division of the communication transaction and the difference of transaction level,a reliability design idea suitable for state network,configure network and data network is proposed.The basis and performance of the design idea are analyzed by establishing response model,power consumption model and delay model.Secondly,according to distinguish of the protocol logic of network protocol,different fault tolerance mechanisms are used.For the protocol control logic of state network and configure network,use spatial triple modular redundancy and time triple modular redundancy.For the protocol transmission logic,use time triple modular redundancy.For the protocol control logic of data network,use spatial triple modular redundancy.For the protocol transmission logic,an end to end detection and error correction retransmission mechanism is adopted.Finally,according to the reliability design idea,I accomplish the design of RTL models and verified the hardware prototype.By analyzing the fault tolerant expectation of the protocol logic,the content is clearly ascertained.The verification strategy of different transaction injection rate is adopted.Through designing compared RTL models,the change of the transaction unmistakable communication ratio under different fault injection rates is studied,and the protocol logic fault ratio is analyzed.Through the test experiment,in the transient fault caused by a single event upset,the three networks can provide more than 99.9% fault tolerance effect,ensuring the reliability of communication.