Research On Multiple Random Transform Split Test Excitation Compression Method

With the continuous progress of integrated circuit manufacturing processes,the scale and complexity of integrated circuits are increasing,resulting in an increasing number of circuit failures.In order to ensure high fault coverage,the amount of test data will also increase greatly.The huge amount of test data not only requires more storage space,but also increases the test application time.Test data compression can greatly reduce the amount of test data,reduce test application time,and also reduce test power consumption.This article focuses on the problem of test data compression.Based on the transformation and splitting method,it mainly does the following work:(1)Split the test set with a random matrix.This method decomposes the original test set into a main component set and a residual set.The main component set consists of the most suitable part selected from the matrix generated by the Linear Feedback Shift Register(LFSR).The residual set consists of tests.The instrument incoming data is obtained after decompression.The main component set and the residual set are XORed to obtain the original test set and are finally applied to the circuit under test.This method compresses the residual set encoding,and the generation of the main component set requires a little hardware cost.Compared to directly compressing the test set,this method can greatly improve the compression ratio of the encoding compression method,and the hardware overhead is also acceptable.Using FDR coding,the experimental results show that the average compression rate of the vector decomposition compression method can reach 75.33%.(2)Use multiple rounds of flipping to increase the compression ratio.The basic idea of this method is to make the test data easier to compress by flipping certain determined bits in the test set without changing the fault coverage of the test set.The specific approach is to use the main component set obtained by method(1)instead of the original test set to perform fault simulation.The main component set will detect a part of faults,and the original test set only needs to detect the remaining undetectable faults.In this way,a large number of determined bits in the original test set can be flipped to a non-determined bit X to obtain a new test set,and then a new test set can be compressed using the vector decomposition compression method.Theoretically,this method can perform multiple rounds of flipping the test set,but the main component set selected in the vector decomposition process will have a corresponding cost in hardware storage.When the second round of rollover is performed,the increased compression rate is already lower than the cost,so only one round of rollover is performed.Using FDR coding,the experimental results show that the average compression rate of the bit flip compression method can reach 81.97%.(3)Bit inversion is used to further increase the compression rate.The basic idea of this method is to make the test data easier to compress by inverting certain determined bits in the test set without changing the fault coverage of the test set.There are a large number of irrelevant bits in the test set.The fault detection ability of the test vector increases with the filling of irrelevant bits,so multiple test vectors repeatedly detect multiple faults.At this point,the test set can modify many determination bits without affecting the fault coverage of the test set.In order to illustrate the effectiveness of this method,we propose an optimized bit reversal algorithm.Using FDR coding,the experimental results show that the bit-reversal compression method can increase the compression ratio by 2.3%on the basis of method(2),reaching 84.13%.