Research On Composite Field Based Higher-Order Masking Scheme And Its VLSI Hardware Implementation

With the rapid development of computer networks,information security has become an important problem that cannot be ignored.The research on attacks and defense direction of cryptographic devices has become a hot topic in the field of information security.The power attacks based side channel attacks technology poses a serious threat to the security of cryptographic chip,and the mask scheme based on composite field has become an effective way to defend power attacks with its unique advantages.Based on the research on S-box constitution arithmetic of composite,we use a low entropy masking method and reuse partial module in GF(24)to reduce the number of multiplication and propose an area optimized generic low entropy higher-order masking scheme based composite field,this new scheme not only decreases the area of combinational logic but also can be applied to any order masking scheme of arbitrary S-box composed of inversion operation.The synthesis results show that the new S-box reduce area by 27.9%,11.9%,5.3% compared with OSWALD,Wang Pengjun and AHN,the security of the scheme is proved.The scheme is applied to the AES encryption algorithm,and the hardware implementation of the scheme is carried out.This article uses the TSMC 60 nm standard technology library,based on the Synopsys DC and the ICC tool,the unmasked,first and high-order masking AES circuits are synthesized.Under the working frequency of 25 MHz,the area of the unmasked,the first and the high-order masking AES is 310.5×309.9?m2,401.9×402?m2,561×560?m2.In addition,the actual power attacks experiments on the masked AES based on the differential power attacks platform can not obtain the correct key.The general low entropy mask scheme based on composite field is designed to reduce the requirement of hardware resources and ensure the application of cryptographic devices in embedded system.