Research And Design For A Secure Processor Model Of Chaotic Neural Network Based On FPGA

With the rapid development of information technology,computer and network technology have been integrated into people's daily life and work.All kinds of important information,from personal privacy to state secrets,may be transmitted by the network information security system,once be damaged,it will seriously affect the development of the society and even the stability of the country.So,how to protect information transmit correctly has been a hot research in the field of computer security.AES is the most popular and universal encryption standard in twenty-first Century.It has many advantages,such as high efficiency,good stability and flexibility.It is widely used in the fields of electronic commerce,encrypted hard disk,network transmission encryption and so on.However,in recent years,there are still some attacks on the AES algorithm,which exposed the defects like simple S-box and single key,so the traditional AES algorithm needs to be further improved.This thesis takes the information encryption as a background,aiming to solve the attack problem of traditional AES algorithm.We design the AES security processing system,and use the chaotic neural network to improve the structure of the S box in order to realize nonlinear chaotic relationship between circular keys,and enhance the crack difficulty of the ciphertext.In the design process,first of all,we use VHDL hardware description language to design and implement AES encryption system based on FPGA.In accordance with the top-down design,the system is divided into encryption module,key expansion module and control module,and the encryption module includes four sub modules,such as S-box transformation,line shift,mixed column and cycle keys XOR.Secondly,in order to solve the defects of the S-box,this thesis uses chaotic neural network to improve the structure of the S-box,and determines the weights of the neural network according to the training samples and the logisitic function,and replaces the traditional S-box with the output sequence;Thirdly,this thesis integrates all the modules into a secure processor model,allocates the system space,and uses Nios II processor to realize the call of each module and the communication control of the computer.Finally,based on the Quartus ? 13.0 software platform,we complete the design of the integrated wiring and simulation test.The test results show that this model can meet the requirement of AES system and improve the security and computation speed of the algorithm to some extents.In this thesis,we study and design a secure processor model of chaotic neural network based on FPGA technology,which can achieve the chaotic characteristics of S-box,and enhance the ability of anti-attack.The system has the advantages of good reconstruction,small occupation of resources and strong practicability.It has a good application prospect in the field of security encryption...