Research On FPGA Implementation Technology Of Image Correlation Matching In Deformation Measurement

With the improvement of camera performance,the resolution of images is getting higher and higher,the amount of information contained in each image is also getting larger and larger,and the data that needs to be processed is also greatly increased and all of them are high-speed images.The software is used to implement image processing.It becomes relatively difficult,with the wide application of high-resolution,high frame rate digital cameras,high-speed image processing technology is increasingly important.This paper focuses on the research about High speed image correlation matching algorithm and its hardware realization.This paper researches the image binarization,median filtering,edge extraction and image scaling and so on,where the highest transmission rate of Camera Link interface can reach 850MB/s,resolution ratio is 2352*1728 and frame rate is 60 fps.Firstly,through it discusses the concept,performance and FPGA implementation method about the parallel pipelining algorithm.Secondly,after doing simulation with MATLAB and considering project difficulty,and hardware cost,image correlation matching algorithm based on normalized cross-correlation search function is selected to image matching.Thirdly,based on parallel pipelining structure,it carries out deployment process to the image processing.For the deployment process,the paper does co-simulation with System Generator to verify the correctness of the design.Finally,it realizes the high speed image processing on hardware platform with Verilog HDL.In this paper,Image correlation matching algorithm and parallel pipelining algorithms are combined.When Camera Link interface works in Medium mode,except the high-speed I/O and Camera Link interfaces,all of the procedures are driven by 80 MHz.It's sufficient to handle the high-speed image data from Camera Link interface and the resource consumption of FPGA is less 60%.More-roads parallel deployment is reasonable and has more performance if the logical resources and memory bandwidth is enough.The design method of this paper is also applies to high speed interface like Coa XPress.