Design Of Neural Network Acceleration Based On Reconfigurable SoC Platform

Nowadays,artificial intelligence algorithm and its applications become more and more popular.The underlying model of artificial intelligence is neural network.Many complex applications,such as automatic control and pattern recognition based on neural networks.Artificial intelligence algorithms make our lives more and more convenient.As the application requirements change constantly,the algorithm becomes more and more complex.With the improvement of algorithm complexity,the requirements of artificial intelligence algorithms for hardware power consumption and speed are also increasing.Using reconfigurable hardware to speed up the computation of neural networks can not only perform reconfigurable hardware's superior performance when performing computationally intensive tasks,but also circumvent its weak performance when performing control-intensive tasks.At first,the paper introduced the development status of reconfigurable hardware technology,discussed related technologies and research status of existing reconfigurable processors.This paper introduced the development of neural networks and the application of neural networks in handwritten numeral recognition.Then,introduced a coarse-grained reconfigurable SoC platform,which has a coarse-grained computing unit and implements hardware acceleration of various algorithms through quasi-dynamic configuration and the reuse of resource.This paper completed the design and verification of neural network-based algorithms for handwritten numeral recognition.The paper realized handwritten numeral recognition with a multi-layer feedforward neural network.The paper completed the design and training of a handwritten numeral recognition neural network model.Then discussed the factors that affected the accuracy of handwritten numeral recognition in the neural network model.The accuracy of handwritten numeral recognition is above 0.98.Based on the above neural network model,the hardware acceleration of multi-layer feed-forward neural network is realized.The paper designed data partition,data storage control,weight address generation,image address generation,and result address generation based on the characteristics of the algorithm.On the reconfigurable SoC platform,the paper realized parallel acceleration.Each arithmetic unit uses a multiplier and two adders to realize the multiplication,accumulation and pipeline.The calculation of each neuron needs the number of cycles of the image pixel points.Finally,the entire design completed the simulation and functional verification based on Vivado 2016.4 and Modalism SE-64 10.4.The paper verified the correctness of the design through the comparison of calculation results and theoretical results by MATLAB.The hardware design supports the acceleration of multi-layer feed-forward neural networks.The number of neurons and the image sizes are configurable.The desien has low hardware complexity,but good parallelism and high throughput.