Design Of MDAC Of Low Power 12bit 50MS/s Pipeline ADC

With the development of wireless network technology and communication technology,the ADC in the system of mobile communication equipment,portable medical equipment,test and measurement equipment et al,not only demand high precision,high speed but also demand low power and low complexity.The pipeline ADC is an optimal choice,because of the perfect tradeoff between the accuracy,speed and power consumption.MDAC is the core block of pipeline ADC,and its performance plays an important role in the system performance of ADC.In this thesis,MDAC of a low power 12bit 50MS/s pipelined ADC is designed.First the effects of those error sources in the pipeline ADC is analyzed in detail.Then in the system architecture,the power model of the pipeline ADC is established to optimize the single-stage resolution.Then the op amp sharing,capacitor sharing,and comparator sharing technique with three-phase clock control is adopted,which not only can save power,but also can eliminate the memory effect and solve the problem of aperture error.Meanwhile improve the sub DAC logic coding circuit to eliminate the impact of additional switches.In the circuit design,a low-voltage two-stage operational amplifier is designed to further reduce the power consumption.A new bootstrap switch is proposed to improve the linearity and speed of the sampling circuit while reducing the power consumption and the area of the layout.Clock circuit,precise control delay,is designed.The design,simulation and optimization of this circuit is based on TSMC 130 nm single-poly eight metal mixed-signal CMOS RF procrss,and the layout area is 250?m × 270?m.The results of post simulation show that SNDR 69.6dB,SFDR 79.2dB,ENOB 11.26 bit are achieved at the expense of 5.27mA current at the 50MHz sampling frequency,with a 24.365MHz,1 dBFS sine wave.