Design And Research On Key Circuit Of 20 KSps Sigma-Delta ADC

Sigma-Delta ADC based on oversampling and noise shaping technology has been widely used as the precision of analog-to-digital converters is increasing in the field of biomedical,communications and Hi-Fi audio.Traditional Sigma-Delta ADC include Sigma-Delta modulators and desample digital filters.Sigma-delta modulator is the core circuit in Sigma-Delta ADC,which move the low-frequency in-band noise to the high-frequency side,seriously affects the speed and accuracy of Sigma-Delta ADC.Compared with the traditional Nyquist structure of the ADC,Sigma-Delta ADC is able to achieve higher accuracy with the lower requirements of the device and the process.This paper uses a top level to bottom method to design Sigma-Delta modulator.By deep analysis of the Sigma-Delta ADC in the oversampling technology and noise shaping technology.According to the clock jitter,charge leakage,switching thermal noise and op amp limited gain,bandwidth,slew rate,output saturation,noise and other non-ideal factors in Sigma-Delta modulator,and their impact on the accuracy of the modulator,corresponding models are built.In this paper,since the system-level model is firstly built and simulated,then according to the simulation result,transistor-level circuit is designed,the circuit design cycle is reduced.The CIFB topology Sigma-Delta modulator system level model of third-order 512-times oversampling rate is established through MATLAB tool.The non-ideal models are added to this system level model.By analyzing the influence of non-ideal factors on the established system,the design requirements of modules in the Sigma-Delta modulator are determined.According to the design standard,the switching circuit,the non-overlapping clock circuit,the bandgap reference circuit,the operational amplifier circuit and the high-speed comparator circuit based on the TSMC0.18?m process are designed and optimized respectively through Cadence IC tool.Adjusting the width to length ratio of PMOS to NMOS in the switching circuit so that they have the same on-resistance at the same on-voltage.The device size of the bandgap reference circuit is adjusted,and the process corners simulation are carried out to obtain a relatively stable temperature coefficient under the worst process conditions.The output stage current of the two-stage op amp is designed reasonably to achieve higher slew rate and bandwidth,and the compensation capacitor size is carefully determined to obtain 65degrees phase margin of the operator amp.A dynamic latching comparator with a preamplifier is designed,which improves the comparator speed.Building up all the modular circuits,combined with the external switched capacitor circuit,The Sigma-Delta modulator integrated circuit with a 20KSps third order 512 times oversampling rate is completed.With carefully considering the device matching and the area,the layout is drawn,whose area is 0.2mm~2.At the power supply voltage of 3V,the digital code stream output by the modulator is subjected to FFT analysis at 65536 points.The final SDNR of the Sigma-Delta modulator which obtained at 20 KHz bandwidth is119.2dB,and the effective bits is 19.5bits,which satisfied the design requirements.