Power Evaluation And DVFS Algorithm Design Based On SCP Multi-core Processor Chip

With the development of CMOS integrated circuits,the quantity of transistors on multi-core chip has generally exceeded 3 billion.But the resulting increase of power density becomes a serious impediment to the performance improvement of processor,raising a challenge to the packaging and heat dissipation of processor as well.Therefore,optimizing the multi-core processor power consumption is an urgent problem in processor design.Most multi-core processors are not always in a fully loaded state,so the part of processor that is idle can be appropriately given less frequency and voltage.This is the most commonly used technology in the area of multi-core processors power optimization called DVFS(Dynamic Voltage and Frequency Scaling).This paper presents the the power consumption evaluation of a high efficiency multi-core SCP processor,and proposes a DVFS scheduling algorithm based on SCP.The main works are:1.Designed the low power management program for the SCP processor in the UBOOT firmware layer and OS driver layer,and completed the control logic of chip voltage regulation based on CPLD.2.Accomplished power consumption evaluation of multi-core SCP processor with multiple application scenarios and low power optimization configuration.3.A dual threshold power adaptive DVFS algorithm,DTPA(Double Threshold Power Adaption),is designed.DPTA adopts the multilevel threshold to control the voltage and frequency.Comparing with single threshold adjusting algorithm which is now commonly used,DPTA can save more power while ensuring performance.On the experimental platform of the SCP multi-core processor running the domestic operating system,experimental results using DTPA algorithm shows that the percentage power saving is higher than that of performance degradation.The performance of these benchmarks are most maintained above 90%,while power consumption can be saved up to 35%.