The Research Of The Integrated Circuit Yield Of Random Defects

Integrated Circuits(IC) is a micro-electronic devices or components. Nowadays, with the continuous improvement in every key area, IC manufacturing technology grows rapidly, the study about yield is also deeper and deeper. Yield precision is a key area in the IC Yield study, the accurate forecast can help the designer make the optimized layout design and also set a reasonable goal to plan time and resources. How to control and ensure a good Yield result is also an important area to apply in the physical manufacturing process.The Random Defects are common defects happened in integrated circuit manufacturing process with very high frequency. This paper mainly focuses on the study of yield impacted from the random defects. It explains the theory of the major utilized IC yield precision models, the design procedures and method, and the key manufacturing yield control factors.This paper has study a lot around the yield precision models, combined the Poisson model and the Negative binomial model together and developed an improved model considering the random defects distribution status. Utilized Matlab to simulate the improved yield precision model, and compared with the actual industrial yield data. The comparison results indicate that the improved yield precision model developed in this pager is more accurate.The yield loss caused by the random defects could be decreased by the layout improvement during the design phase and the yield control during the manufacturing process. This paper optimized the design layout through the adjustment on the critical area of open circuit and short circuit. Each layer in the landscape design should consider the key area of the optimal set. In the process of IC manufacturing technology, mainly through the clean room control, the key process control and timely control and removal of random particles. Many online machines and the key statistical data analysis are required to support and ensure timely finding of defects occur on each steps to avoid the defects left to the next node, which might cause more serious impact.This paper will introduce and analyze the random defects distributions and the current yield prediction model, up to that, the paper will introduce the detailed work and yield improvement solutions during the IC design and manufacturing stage, build up a improved prediction model and compare with the other models and the actual manufacturing data.