The Design And Implementation Of Highspeed Serial RapidIO Interface

Serial RapidIO technology has unique advantages in signal interchange of inside of high speed embedded system.RapidIO has powerful signal transport ability.Meanwhile,RapidIO has detailed rules in all aspects so that it can ensure reliability of high speed signal transport by hardware circuits.Furthermore,RapidIO has very low dalay and high bandwidth.It supports interconnection topology structure for any type and greatly improves the flexibility of the system.Therefore,RapidIO technology has been widely used.Firstly,the paper introduces the protocol specification system of RapidIO.The paper specifically analyzes basic level structure,operation and packet format of RapidIO protocol specification,and summarises the function and structure of logical layer,transport layer and physical layer of RapidIO protocol specification in detail.The physical layer hardware design of RapidIO interface is completed in this paper.The physical layer is divided into four parts: physical coding sublayer,serial protocol layer,Buffer and physical media attaching sublayer.The design of physical coding sublayer is divided into 8b/10 b encoding and decoding module,idle sequence generating module,lane synchronization state machine and 1x port initialization state machine.The design of serial protocol layer is divided into CRC-16 generating and checking module,control symbol generating and checking module,transmit state machine and receive state machine.In the design of CRC-16 generating and checking module,due to the traditional CRC-16 producing scheme,the situation of different end boundary in the last cycle increases the design difficulty of the CRC calculation;and in CRC-16 checking scheme,traditional schemes have too long critical path or take up too much resource.Aiming at these problems,an improved CRC-16 generating and CRC-16 checking scheme are proposed dividly.The design of Buffer is divided into transmit Buffer and receive Buffer module.The physical media attaching sublayer directly uses high performance Xilinx SerDes IP.The design of RapidIO interface supports transmission rate of 3.125 Gbaud rate for single lane(1x).Finally,the paper using Hardware Description Language Verilog to complete the RTL code of each module of RapidIO interface,and using Modelsim simulation software to verify the function of interface of each module and the whole interface.Simulation results show the validdity and feasibility of design of the paper.