Research On The High Speed Receiver Circuit Of JESD204B

In view of the mismatch problem between the FPGA speed and converter processing speed,FPGA manufacturers have been discussed Gigabit SerDers interface topic for many years and have recognized the necessary for large and fast channels,and thus take full advantage of SerDes bandwidth.Under such a background,the JEDEC Committee released the JESD204 B protocol in 2011 as the latest standard for the converter industry,which is primarily used for high-speed serial interfaces between data converters and logic devices(FPGAs/ASICs).Compared with the traditional CMOS interface and LVDS interface,JESD204 B interface has obvious advantages in the power consumption,the number of pins and other aspects.JESD204 B solves the layout and routing complexity of parallel interface,multi-chip synchronization,multi-chip deterministic delay problems and provides an effective solution for wireless communications,medical imaging and other modern high-speed signal processing fields.The industry agreed that the high-speed serial interface based on JESD204 B protocol is the guarantee of improving the data transmission rate of communication system.After JESD204 B released,it quickly caused the international well-known converter manufacturers attention,after several years of research and development,at present,ADI/TI have released a variety of chips internal integrated JESD204 B interface,but in china there is no complete independent intellectual property rights of products and basically using special processes such as GaAs(gallium arsenide)process to achieve the interface circuit.Based on the deep understanding of JESD204 B protocol,this paper presents a receiver circuit design scheme for the high-speed Serdes interface based on JESD204 B protocol,which mainly covers the data link layer and transport layer of the protocol.The research idea is combining the protocol specification and the existing related chip manual,conducting a reasonable division for the functions specified in protocol,and finally getting the circuit structure fully meet the requirements of protocol.In order to meet the channel rate of up to 10 Gbps,the quad byte parallel design method is adopted to reduce the requirement of the highest clock frequency.At the same time,the parallel topology of data processing and synchronous control also improves the running speed of the circuit.For the key technology of initial code group synchronization,initial lane synchronization,character replacement,self-synchronization scrambling and 8B10 B coding,this paper gives the concrete design scheme and detailed description.All modules of the design have been simulated by Modelsim and synthesized by Design Compiler,The results show that the circult correctly completed the functions of the data link layer and the transport layer of the protocol specification,and the max circuit frequency achieved 250 Mhz which can match serial channel rate up to 10 Gbps,fully meet the requirements of the protocol.This paper presents a specific JESD204 B receiver circuit solution,to a certain extent,which can promote the domestic JESD204 B research and development.