Design And Implementation Of A Circuit For Testing The Performance Of Standard Cell Library

Integrated circuit is the core of today's social information industry,it is the most important reflection of national high-tech,and also the important guarantee for economic development and national security.With the development of Moore's law and the scale of the integrated circuit design is more complex,integrated circuit need reusable and reliable IP library support,standard cell library is one of the most basic IP library,its design determines the performance of the chip.This paper design a circuit for testing the performance of standard cell library,and introduces the design process in detail,comprehensively evaluate the speed,area and power consumption of SMIC 0.18?m standard cell library,also compare the performance different between the two versions standard cell under the same process after synthesis,effectively improve the efficiency of the standard cell library evaluation and the reliability of evaluation results.This paper first introduces the existing standard cell library testing methods,highlighting the advantages of the circuit design in this paper,and then discusses how to use the current mainstream ASIC design process to complete the circuit design.This design mainly use of Synopsys' s EDA tools.During the design process,doing the function simulation of the RTL level and the dynamic simulation with delay by VCS;using the Design Compiler to synthesize circuit;using IC Compiler to do automatic placement and routing;using Prime Time to analysis static timing;using Formality to do formal verification.After tape-out,the test result show that the performance testing circuit can work normally,prove the rationality of the whole performance testing circuit design and successful completion of the desired design objectives.