Design And Implementation Of High-speed Multi-channel Digital Beamforming System

Digital beamforming(DBF)is a kind of signal processing technology realized by using multi-sensor array in modern radar signal processing system.On the one hand,making a DBF process in a certain direction could maximize the signal in this direction.On the other hand,using the DBF technology can effectively suppress the spatial interference and enhance the signal noise ratio.Based on the principle of wide-band and narrow-band beamforming,this paper has given a detailed description and simulation of the implementation of radar array system in the case of high-speed multi-channel.There are a large amount of advantages in FPGA,such as the large number of I/O,parallel processing ability,high customization degree and fast data transmission speed.Therefore,in this paper we used FPGA as the data flow control center of the system to realize the acquisition,processing,control and forwarding of the data.At the same time,this paper provided a specific assessment method for the amount of resources which was required for the FPGA to meet the actual requirements of the project.And with regard to the resource usage,the layout and program framework design of the selected chip model and FPGA on-chip resource were given in this paper.Finally,the working principle of Rocket I/O high-speed communication module was illustrated.Also,the important module in GTX transmitter and receiver,the use of IBERT tool and the solution of GTX common problem were described in detail.On the other hand,some new solutions were put forward about the problems in the actual project realization process in this paper.Firstly,a method was presented to realize the narrow-band beamforming algorithm for multiple antenna elements on FPGA,and the application of the method was verified in practical engineering.The simulation and verification were carried out on both of the wide-band beamforming algorithm based on adaptive optimization algorithm and array channel mismatch correction algorithm,and the parallel algorithm implemented on the FPGA was proposed.Secondly,a stability test and solution were presented,which was applied to the high-speed communication among the optical fibers,the communication among the multi-chip FPGAs or the high-speed communication between the FPGA and the host computer or other signal processing modules.Finally,some solutions were presented to solve some common problems in the complex timing logic design,which further kept the stable operation of the FPGA.