Design Of Low Noise Amplifier For Hall Sensor Readout Circuit

In recent years,with the rapid development of the Internet of things,driven by the strong rise of the whole industry chain from chips,sensors,wireless modules,network operations to platform services,software development and smart devices.As the basis of the Internet of things,the sensor technology has gradually penetrated into all aspects of people's lives.Among them,with the advantages of small size,high sensitivity,strong diamagnetic disturbance and so on,the Hall sensor has occupied an important market share and become the world's third-ranked sensor products.In view of the wide application of Hall sensors,the processing and research of its output signal has become a key problem.Based on this,in this paper the post-processing circuit will be studied.Hall sensor readout circuits mainly include low noise amplifiers and analog-to-digital-converter(ADC).This paper focuses on the front-end design of the readout circuit—a low noise amplifier.The design of the front-end amplifier is a key part of the readout circuit,and its characteristics directly determine the final result of the readout circuit.As the size of the MOSFET device decreases and the amplitude decreases,the low-frequency noise characteristics of the circuit become more and more serious.The Hall sensor mainly works in the low frequency range,which is greatly affected by low-frequency noise.Therefore,in order to reduce noise parameters,this design adds chopper technology.In the new structure,the design of the Complementary Metal Oxide Semiconductor(CMOS)switch chopper can effectively reduce the low-frequency noise,and can reduce the channel charge injection effect on the system;Then,it design a two-stage fully differential structure with PMOS as a differential input,which can suppress common mode noise;Finally,in order to ensure a stable differential output common mode level,a single stage differential common mode feedback circuit is designed,which reduces the power consumption and further suppresses the noise.In order to change the gain and increase the load carrying capacity,four gain switches and buffers are added to the circuit.The layout design adopts full customization,and the layout of the layout is optimized continuously to reduce chip area and power consumption.The design uses SMIC 0.18um CMOS process.Based on the Cadence simulation platform,the simulation results are as follows:In the 3.3V power supply voltage,the equivalent input noise is 22.41nV/sqrt(Hz)@100Hz,op amp chip area of 0.47 x 0.52mm2,the overall readout circuit chip area of 1.1 x 1.5mm2.After adding chopper technology,the circuit flicker noise is greatly reduced,which is very suitable for the Hall sensor detection circuits.