Design And Implement Of Point-to-point Transmission System Of Fiber Channel Based On FPGA

With the increasing demand for a large amount of data transmission in a short time,the parallel transmission will meet the bottleneck with the increase of the working frequency.In the high frequency and long distance transmission,even a slight difference in the lengths of the parallel signal lines will result in a large phase difference at the receiving terminal,and also the signal crosstalk.Although some measures can solve these problems,the cost is usually very heavy.In high frequency and long distance transmission,serial communication has incomparable advantages compared with parallel transmission.With the semiconductor process technology improvement,the working frequency of serial devices can be very high,and there is no problem of crosstalk as in parallel communication,such that the transmission bandwidth of the single signal line can be larger.Compared with the common coaxial cable,the optical fiber has many advantages to serve as the transmission medium.Relying on the transmission of light which is reflected back and forth in the pathway,the signal is difficult to be interfered by the electromagnetic wave.The transmission bandwidth can be very high,and is suitable for the situation for transmitting a large amount of data.The signal loss is so low that the lane needs few signal relay stations.In this thesis,the FC-FS protocol of fiber channel is analyzed in detail,and the FC-FS protocol is used to explain the FC frame format and the basic control characteristics of fiber channel.Based on the analysis of the fiber channel protocol,this paper designed and implemented the physical layer,coding-decoding layer and frame transmission layer of the fiber channel.The physical layer is realized by the RocketIO core and the high-speed photoelectric conversion module of the development board.Frame coding-decoding layer enables the transmitting terminal to realize the coding and transmitting of the data of 32 bits and realizes the alignment and decoding restoring of the receiving terminal data.The frame data and frame information are cached separately,and the assembly of the transmitting terminal frame and the extraction mechanism of the receiving terminal frame are realized.When the verification on the receiving terminal data have error,a mechanism of error retransmission is designed and simulated.The channel state controller is realized,which provides a high speed channel for the frame transmission and can handle the common abnormity in the transmission.The buffer state controller is implemented,which can send frames to the other when the buffer space is enough.Through the above modules,the design implemented the transmission and extraction of frames between two nodes.The design is based on Xilinx Virtex 5 platform development,with the help of Isim and other simulation tools for the verification of bottom-up.With the help of debugging tools such as nLint and Questa CDC,the problem of potential cross clock,which is difficult to find by the waveform simulation tools,is found and solved,thus improving the stability of the system.The board debugging is performed on the design via Chipscope,which verifies the correctness of the design.