Process Optimization On Interlayer Dielectric And Properties Of LTPS TFT

Low Temperature Polycrystalline-silicon Thin Film Transister(LTPS TFT)has made considerable progress in not only the Liquid Crystal Display(LCD)but also the Active Matrix Organic Light-Emitting Diodes(AMOLED).The ultra-high resolution display requires exactly control key dimensions of the device and fine uniformity,and it has become the bottleneck to the process capability and product yield,which makes it a great challenge to device performance enhancement.In the trend of ultra-high resolution,the process optimization of LTPS TFT interlayer dielectric was studied,which aimed at promoting the process ability,reducing the yield loss and improving the production quality.So the specific investigations of this article are as follows:(1)The via profile of interlayer dielectric was studied by dry etching method with different 02/CF4 gas flow ratio in main etch process.The results showed that:1)The tilt angle of the via profile had a linear relation with 02 flow ratio,which decreased with the 02 flow ratio increased.2)There were angle stratification between dielectric layer with the 02 ratio increased,and the stratification phenomenon got increasingly severe.(2)The etch rate selectivity of SiOx and p-Si was studied by dry etching method with different CHF3?H2 total gas flow in over etch process.The results showed that:1)The etch rate selectivity was better when CHF3?H2 total flow increased,as well as the SiOx etch rate increased and the p-Si etch rate decreased.2)The etch uniformity both SiOx and p-Si were worse as the total gas flow increased over 1050sccm.3)When the CHF3?H2 gas flow came to 750sccm?300sccm,we got not only a high etch rate selectivity but also fine etch uniformity.(3)A new method and optimum process based on dry etching as the main etching step assisted with wet etching to optimize the via etch profile was investigated.The results showed that:1)The optimum process was obtained when dry etching end at the time of EPD+35s,and the wet etching time of 50%over-etching.2)It had excellent control of via etch profile?feature size and high etching selectivity.By this method we solved the over etching and etch residual problem completely,and the yield loss of via etching defect rate reduced by 73%.(4)The LTPS TFT devices were made based on the etching optimization to research the device performance.We also analysised the p-Si film composition after via etching with XPS test to explore the impact on device performance.The results showed that:1)The contact resistance of source-drain electrodes decreased an order of magnitude and the ON-state current raised 15%.2)The contact resistance.reduced because that could avoid the plasma damage,p-Si surface being oxidized,and being polluted by etching by-products.3)It got a great improvment in the uniformity of device electrical characteristics.