Design And Implementation Of A Virtual Platform Based On SPARC V8 Architecture

With the rapid development of IC manufactural capacity and extended requirement for new applications, the design complexity of SoC grew dramatically. Due to the limitations of RTL simulation mechanism, the traditional SoC design flow will consume a long time for larger design and thus cannot satisfy the requirement for time to market. The virtual platform, which is based on the ISS, is proposed to speed up the simulation and provides an environment for the SoC system level verification and embedded software development before the completion of RTL platform.In this paper, to meet the need of SoC architecture design and embedded software development, an extensible framework is proposed to model the virtual platform. An efficient hierarchical architecture is used for the main part of the framework, namely, the UTM system, to satisfy the requirement of high performance and fine modeling granularity in virtual platform. The architecture introduces the dual-queue structure to manipulate the high-frequency event such as the instruction execution, while the hashed timing wheels is adopted for the low-frequency peripheral I/O operations. The system is configurable and independent from the virtual platform. Based on the interfaces provided by the framework, the SPARC V8 based transaction level SoC verification platform, which contains the ISS, AMBA bus function model, UART, timer and other I/O devices, is modeled to verify the reasonability of the framework.The uC/OS is replanted to SPARC and task switch, interrupt handle, UART driver, and dynamic memory management are implemented. The test results indicate the functional correctness of the transaction level SoC verification platform and the multi-task environment in uC/OS works well on that platform. The performance of the UTM system without any workload can reach up to 300 MHz, while with the SPARC based platform, the ISS can execute instruction at nearly 120 MIPS, which is 2 to 3 times faster than what can be done in real hardware platform.