The Design And Implementation Of Prefetch Structure In The XMC Interface Of YHFT-XDSP

Nowadays, the Digital Signal Processor(DSP) has been more and more widely used, and it's performance has been upgraded frequently. However, the “memory wall” problem has become the challenge of design of DSP. Multiple level memory structure is commonly used to resolve this problem, in which the “Cache+RAM” two level structure is popular. Although, the stall caused by Cache miss influence the efficiency of processor badly. Many studies indicate that the probability of cost of Cache miss could be reduced by prefetch, but there is no high performance prefetching structure that is widely acceptable yet. Therefore, the design of a low-cost and effective prefetching structure is a hot question who is pondered Continuously.“YHFT-XDSP” a high performance DSP which is developing independently by NUDT, whose basic frequency can be up to 1 GHz. The “Cache+RAM” two level structure is used on it, so the proportion between Cache and RAM can be configured by users. The interface between core and outer include Extended Memory Controller(XMC) and External Register Interface(ERI). Among them, XMC is the main path from Level 2 Memory(L2) to Public Memory Controller(PMC). Additional, functions of Address Extension and Memory Protection are provided by XMC.Based on the character of XMC interface on “YHFT-XDSP”, this paper study in the desigh of prefetching structure, and achieves following works.First, this paper designs a separating prefetching mechanism with a data filter based on the common character of Cache miss and four modes of L2 miss request. The probability of data Cache miss is higher and its spatial locality is worse. So, the data filter is designed to filter the invalid prefetch in the condition of bad spatial locality, and the accuracy of prefecth is strengthened. Asidely, prefetch can assist L2 miss request by an additional pre-request according to four modes of L2 miss request.Second, this paper achieves the implement of a pipelined prefetching structure based on the XMC interface of “YHFT-XDSP”, and the controlling logic working with the XMC interface. When a L2 miss request arrive, data will be output from prefetching buffer, if it is hit the request, so the Cache miss cost is reduced. The speed requirement for interface is lower than for Cache. therefore, compared to a prefetching structure based on Cache, a prefetching structure based on XMC interface is more scalable and cheaper.Last, this paper use methods of software and FPGA simulation to validate the function and performance of design. And synthesis optimizes is achieved too. The result showed the time of some typical test programs running on FPGA is reduced up to 9% with a prefetching structure. So, the performance of system is improved evidently.