A Design Of Cache Based On STT-RAM

Compared to traditional DRAM and SRAM, the novel non-volatile memory(NVM) technology possess a large number of advantages, such as high integration density, low power consumption and non-volatile storage capability, etc. It is thus expected that NVM technology will challenge the established storage system, and bring new opportunities for the development of computer storage technology. Compared to other candidates of NVM, STT-RAM is highly considered for its advantageous attributes including high access speed, high storage density and long endurance. As a result, it has been employed as one of the promising candidate to replace the typical SRAM in the fields of high-speed cache. In this thesis, the research work mainly focuses on the analysis and design of STT-RAM based reconfiguration high-speed cache. The main contents include:Initially, this dissertation introduces the function of high-speed cache within computer system, and its influence on computer performance. Then, the advantages and disadvantages of STT-RAM in storage density, access delay and programing energy are introduced. Based on these characteristics, this dissertation investigates the superiority of STT-RAM based high-speed cache and the problems need to be solved.Secondly, compared to SRAM, STT-RAM based cache still has disadvantages, such as long write delay, high write energy and short endurance. Considering these problems, this dissertation propose a new cache architecture and migration strategy that can make full use of STT-RAM's large capacity and SRAM's fast speed. While improving the performance of cache, the proposed architecture could over-write the STT-RAM, which will bring new problems of high dynamic power and limited endurance of write operation. To solve these two problems, this dissertation designs a read-before-write programming method and dynamic reconfiguration strategy, which will minimize the influence of these two problems on system performance by reducing the write operation and static power consumption.Finally, a series of simulation experiments were designed and implemented to evaluate the proposed cache architecture. The simulated performance of proposed STT-RAM based cache is compared with previously published region based hybrid cache architecture(RHCA) method in terms of the hit rate, performance, energy consumption.The innovation of this thesis is to propose novel STT-RAM based cache architecture and improvement design, and solve the problems of established STT-RAM in unbalanced read/write delay, access speed gap with SRAM, high write energy, and limited write lifetime.