The Design Of New Algorithm For Adaptive Noise Cancellation Digital System

Adaptive digital system is a digital system to eliminate the noise in the communication system. The implementation of the adaptive algorithm in the hardware platform is a part of the project must be done, that is, the design of the adaptive digital system. The papers and specific engineering, adaptive cancellation adaptive algorithm for digital system used mainly fixed step size LMS algorithm, the classical variable step size algorithm is applied in the speed requirements of the adaptive cancellation of digital system is hard to achieve, there are resource consumption is too high and the computation time is too long and so on. Currently implemented in the adaptive cancellation algorithm of digital system is mainly fixed step size LMS algorithm and classical Kwong variable step size algorithm and the normalized least mean square(LMS) algorithm is applied in the speed requirements of the adaptive cancellation of digital system is hard to achieve, there are resource consumption is too high and the computation time is too long and so on. Object of the research work in this paper is used in communication system, especially the frequency hopping radio system adaptive cancellation algorithm design of digital system, so the convergence time of the algorithm is the main concern, this paper presents the FPGA truncation variable step size algorithm based on, contrast application in FPGA adaptive cancellation classic algorithm in digital systems, the truncation variable step size algorithm improvement in convergence speed, can better solve the frequency hopping communication system in time on the problem.In this paper, the basic principle, structure and application of the adaptive cancellation system are analyzed. Then, the adaptive filter and the digital system based on the adaptive filter and the adaptive algorithm are introduced. Then through the analysis of the fixed step size LMS algorithm, Kwong variable step algorithm principle and analysis of digital systems design guidelines and a new variable step size algorithm based on FPGA adaptive canceller digital system, herein named truncation algorithm of variable step size is proposed. Then in MATLAB of fixed step size LMS algorithm, Kwong variable step size algorithm and truncation variable step size algorithm to simulate and compare. Finally on the Altera's Quartus13.0 platform body are adaptive to digital system with the fixed step size LMS algorithm and truncation variable step size algorithm simulation, combined with the requirement of practical system, to the influence of various parameters on the system do the detailed analysis and simulation output data to Matlab simulation analysis. The conclusion: 32 order truncation variable step size LMS algorithm for digital system can achieve the maximum clock frequency is 66.65 MHz, highest frequency of data input signal to 16 mhz and after 400 data cycle can reach about 4 d B offset, after 600 data cycle can reach about 60 d B offset, compared with that of the fixed step size LMS algorithm and improved, with a certain practical value in engineering.