LDPC Codec And Its FPGA Implementation

Low Density Parity Check code(LDPC code) is a kind of channel coding technology, proposed by Gallager in 1962, based on a sparse parity check matrix, just like Turbo codes, it has excellent performance approaching Shannon limit. The channel coding technology is one of the key technologies of the communication system, thus designing high-speed LDPC codec has become an important field of research.This paper introduces some knowledge of LDPC codes, then study several constructors of LDPC code check matrix. At the same time it introduced the LDPC encoding and decoding algorithms and principles of design corresponding encoding and decoding methods using FPGA(Field Programmable Gate Array). As for encoder, according to the characteristic of a quasi-cyclic double angle check matrix, use cyclic recursive algorithm for optional(1008,504) QC LDPC code to achieve a coding simulation output, the maximum clock frequency up to 220.15 MHz. As for decoder, using a minimum correction and decoding algorithm, choosing partially-parallel decoder architecture considering both hardware decoder system throughput and resource consumption. Selecting a preset maximum number of iterations of the decoding key information and quantization scheme by simulation, as well as designing decoder main function modules, including an information initialization module, a variable node calculation module(VNU), check node operation module(CNU), an information storage module, the main controller module and so on, achieving a simulation output, the maximum clock frequency up to 188.64 MHz, and for a single decoding module can reach 360 Mbps throughput.