The Realization Of Digital Transceiver Based On GFSK Modulation

Wireless communication system composed by the transmitting device and receiving device, wireless channels, using wireless electromagnetic waves realize the information and data transmission. Compared with cable communication system, wireless transmission is more flexible. The wireless signal from a transmitter sends to many receivers without a cable. The digital transceiver is the core part of the wireless communication system.FSK is a modulation method used in earlier information transmission. Its main advantage is: it is easy to implement, resistance against noise and attenuation of good performance, low power consumption. It has been widely used in the low speed data transmission. GFSK modulation can change the 3d B bandwidth at the same time of constant amplitude that is important for the wireless communication system. Therefore, GFSK demodulation technology is widely used in digital transceiver. The main research work and achievements of this paper summarized is as follows:Modulation mode uses GFSK direct modulation. The digital signal filtered by gaussian lowpass filter, repass third-order Delta-Sigma modulator for decimal frequency division. Finally the output signal add on the VCO of PLL frequency synthesizer to complete modulation.Encoding mode uses hamming code and CRC code. Hamming code has very good error correction ability. CRC code has good error detection capability. Through the adoption of code can effectively reduce the error rate of digital transceiver.Filter mode uses the CIC filter and half band filter cascade structure. CIC filter by adopting cascade structure improves the filtering performance. In terms of filter algorithm, DA algorithm is the most efficient and suitable algorithm for the ASIC design. Because this algorithm can reduces the chip area.Code synchronization is realized by using digital phase-locked loop that constituted by digital phase digital phase-locked loop(DPD), digital loop filter(DLF) and digital voltage controlled oscillator(DCO).The synchronization is realized by adding and subtracting clock. But synchronization result is bad.Design by adopting variable clock and gating clock technology reduce power consumption. The watchdog can improve the reliability. Adoption of these technologies improve the performance of the digital transceiver.This design go through MATLAB simulation, Verilog HDL RTL coding, Modelsim SE simulation and FPGA validation.So, the results can meet the design requirements.