An Low Power ECG ASIC With Weak-Strong Hybrid Classifier For Arrhythmia Detection

Arrhythmia is one of the highest among sudden death.With the development of ECG technology and wearable devices,the cardiac real-time monitoring technology is beginning to take shape,which is of great significance for the prevention of arrhythmia.However,it is limited by the battery-powered mode of wearable devices,The power consumption of the apparatus becomes one of the main challenges of its design.Traditional wearable ECG devices collect the ECG information,and upload to the remote cloud for processing through wireless transmission technology.The wireless transmission causes a huge energy consumption,seriously limiting the battery life.With the development of machine learning technology,the wearable ECG device integrated with self-diagnosis function starts to appear.How to reduce the power consumption of the device under the premise of ensuring diagnosis accuracy has become a new research hotspot.In this thesis,we propose a cardiac arrhythmia detection circuit with integrated machine learning engine,which can finish diagnosing at node-side.The main contents and innovations in this paper are as follows:1.ASIC circuit including machine learning engine is designed.The circuit includes signal preprocessing part,feature extracting part and machine learning engine,which can realize node-side diagnosis.2.A low-power architecture based on hybrid classifier is proposed.Based on the QAR feature proposed in this thesis,which can effectively reflect the information of cardiac pathology,a low-power linear classifier is designed.The hybrid classification architecture is first categorized by a linear classifier,and its uncorrected heartbeats are dealt with more accurate but high-powered SVM classifiers.Because most of the heartbeat samples have obvious features,the linear classification can do the diagnosis,and the SVM classifier does not need to be enabled so that the low power consumption of the classifier is achieved.3.Proposed low-cost SVM learning engine implementation method,the SVM learning engine involved in the divider,square exponent and exponent operator have been optimized,which greatly optimizes the circuit area.Implemented in SMIC 40LL CMOS process,the processor has a total area of 0.12mm2.It achieves 1.97uW power consumption in WLC mode and 3.76uW in SVM mode under 1.1V voltage supply and 10KHz operating frequency,with energy dissipation of 6.8nJ/30.3nJ per beat classification for the two modes,respectively.The overall accuracy for MIT-BIH arrhythmia database is 98.2%with energy reduction of 41.7%.