The Research And Hardware Implementation Of Hyperspectral Image Compression Method Based On 3D-LBT

In recent years, the high resolution of hyperspectral sensor has led to a significant increase in the volume of hyperspectral image data, so that the Gao Guangpu image compression becomes more and more important and necessary. Among them, the high spectral image compression method based on transform is one of the typical methods, which has the characteristics of lossy and lossless, and is conducive to the realization of the hardware. In this paper, we study and improve a Three(Dimension-Lapped Biorthogonal Transform 3D-LBT) based lossless hyperspectral compression algorithm and its software implementation, and the key modules of the hardware implementation.Firstly, hyperspectral compression algorithm based on 3D-LBT is designed, which includes 3D-LBT, prediction algorithm and encoder. For the prediction part, on the basis of research on the 3D-LBT transform coefficients and low-frequency coefficients and DC coefficients three coefficients of correlation, aimed at improving the has three modes: differential pulse code modulation(differential pulse code modulation, DPCM) algorithm. For entropy encoding section, the optimization design of the range coder and the basic theory and the technical realization method, before the encoder Histgram packing to convergence prediction operation with an encoder, and in order to further improve the coding performance before the encoder increases the positive mapping operation. After for the cumulative frequency statistics within the range coder algorithm improved. Then the algorithm is implemented on Studio Visual 2012 platform, and the average compression ratio of calibrated scene Yellowstone 0, 3, three, 10, 3.603 is verified.Secondly, using the VHDL(VHSIC Hardware Description Language) to achieve the compression algorithm in prediction and coding module, and in its internal use pipeline structure of each sub module organization, the use Modelsim10.1d RTL(Register-Transfer Level) simulation of the compiled module, and after the comprehensive of gate level simulation, that each module on the pipeline structure is used in order to pave the way. Comparison of the results and pipelined architecture, the modules according to, after the use of Quartus II to carry on the comprehensive, the RTL and gate level simulation using Modelsim10.1d, using interception after Yellowstone calibrated scene 0, 3, 10, three pieces of hyperspectral image after transformation software the resulting transform coefficients as a data source on the of the verification, reached a throughput of 280.6Mbps, and will be the result with software income gave the same results.Finally, based on EP2S130F1020I4 FPGA hardware platform to 100 MHz clock to verify the algorithm in this paper the encoder module, simulation and software system with the same results, verify the validity of the hardware system.