Research And Design Of High Density SPAD Detector Based On Shared Deep-n-well Structure

With the development of detection technology, more and more fields need to detect and process extremely weak optical signals with very high speed. All kinds of new materials as well as detection methods have been used in the detection of weak optical signals. Among them, the single photon avalanche diode (SPAD) has attracted much attention with its high response speed, high sensitivity, high gain coefficient, and so on. In addition, the SPAD array detector has become the development direction of the imaging technology because of its high response speed, low power consumption, and high detection efficiency. At present, the difficulty in the development of SPAD array is how to reduce the area and improve the fill-factor of the array without affecting its performances. And in this paper, we will focus on this issue for further research.First, this paper presents a high-fill-factor (FF is the ratio of photo-sensitive area to total imaging or pixel area) SPAD structure, where four SPAD devices share the same deep N-well, and fabricated in a conventional 0.18 μm CMOS technology. A honeycomb structure is also used in this array cell to improve the fill factor. By calculation, the overall fill-factor of the array cell is 57%. Various methods, such as the virtual guard ring, are also used in this structure to reduce the crosstalk caused by the shared deep n-well. The key parameters such as Dark Count Rate (DCR) and Photon Detection Efficiency (PDE), are calculated to analyze the important statistical performances of the proposed SPAD structure.Second, this paper designs a compact gate-mode quenching/reset circuit and an analog-counting circuit that is based on the capacitance discharge. In the gate-mode quenching/reset circuit, we use only 8 small transistors to achieve fast quenching and reset of the SPAD. And in the analog-counting circuit, we achieve 9-bit linear-count with a 500 fF capacitor. The area occupied by this pixel unit circuit can be minimized.Third, an embedded array designing is proposed. In this array, we insert the quenching/reset circuit and the analog-counting circuit into the spaces among four adjacent SPAD array units. With this scheme, the area of a 4 × 4 array is about 240 μm× 240 μm, and the fill-factor of the chip can reach up to 88.33%. Compared with traditional SPAD array, this SPAD array greatly improves the utilization rate of the chip and reduces the production cost.