Study And Design Of A High Speed And High Precious Track/Hold Circuit

The track and hold circuit (THC) is a critical part of high speed analog-to-digital converters (ADC). Usually it is used at the front-end of ADC to take samples of its analog input signal and hold these discrete samples for quite enough time for ADC to accomplish quantification and coding. Its resolution and sampling rate determines the highest resolution and highest sampling rate of the ADC, so the performance of THC is crucial to the ADC. ADC is developing rapidly towards high speed to satisfy the need of high-frequency communication technology, software defined radio, radar and so on, this means the research of high speed THC is also becoming more and more significant.Both the application background of THC in the folding & interpolating ADC and the characteristics of different THC architectures are discussed in this paper, and the open-loop two channels time-interleaved structure is selected to design THC, which can be applicable in the 10bits 1.6GSps folding&interpolating ADC.The limitation of resolution in the open-loop THC is analyzed, and some methods are discussed to improve the non-ideal characteristics, such as high linearity bootstrapped switch, source degeneration topology, adding dummy MOSFETs to absorb injected charges and so on. Input buffer sharing and master clock method is introduced to diminish the mismatch between the two channels; an input buffer adopting replica part with 3dB bandwidth=5GHz, SFDR>77dB is proposed; a fully-differential amplifier with fully-NMOS is designed as the 2nd buffer, replica basing circuit is added to stabilize the output common voltage; positive voltage charge pump, negative voltage charge pump and reset pulse generator which are based on cross-coupled MOSFETs are also proposed.The circuit is designed and simulated using Cadence Spectre and 0.18μm CMOS process, the supply voltage is 2V. Simulation results with coherent sampling method show that:with 1.6GSps Nyquist-rate sampling,600fF load and 800mVpp sinusoidal input, its SNDR reaches 72.3dB and ENOB is above 11.7 bits. According to the simulation results, the designed THC could be applied in 10 bits and 1.6GSps ADC.