Design Of Analog Delay Cells Integrated Circuit

With the rapid development of Integrated Circuit (IC) industry, signal timing require-ments of high-speed hybrid systems is increasing. When designing some circuits, compensate the delay time between different paths and solve clock skew by adding some delay cells. De-lay cells have been widely used in equalizer, antenna array, delay locked loops and so on. The critical role of the delay cell in these systems decides their performance, so delay cells be-come an important area of the research.The paper designs a delay cell circuit based on delay locked loop (DLL). DLL is com-posed of four basic modules, phase detector, charge pump, loop filter and voltage-controlled delay line respectively. This design adopts frequency dividers to solve the working frequency’s restriction of the PD.Meanwhile, the introduction of single transistor solves the error locking and harmonic locking in conventional DLL.The delay cell adopts source coupled differential structure to achieve a smaller delay time and improve the frequency of input signals.The clock generation circuit has been designed in a 0.13 μm CMOS process by IBM. The total area is 520x720μm2. The post simulation results show the input frequency of the DLL is from 3GHz to 5GHz. The delay line contains ten delay cells. When the input signal is 5GHz, the delay line outputs ten clock signals whose phase internal is same, and each cell’delay time is 20ps. When the input signal is 3GHz and 5GHz, the static phase error of DLL is 2.6ps and 8.5ps respec-tively, and the peak-to-peak jitter is 3.3ps and 1.7ps respectively.The DLL has a negative feedback regulating function.Under the different process corners, the delay of it keeps invarious. The paper designs a high-precision delay cell. The DLL acts as a control loop of out-loop delay lines and the out-loop delay lines share one control voltage with the DLL. The delay cell adopts active inductor shunt peaking, improve the bandwidth to delay the high frequency signal. The design has also been designed in a 0.13μm CMOS pro-cess by IBM. The total area is 585x720μm2. The post simulation results show the input fre-quency of the DLL can reach 1.67GHz. Eight delay cells are included in the delay line. The delay of single delay cell is close to 18.75ps and the error is less 0.5ps. The design of this pa-per about a clock generation circuit and a high-precision delay cell has some significance in the research of DLL and delay cells in the future.