Research Of Last-Level Cache Management For Hybrid Main Memory

The SRAM/DRAM based memory has become energy and scalability bottlenecks of contemporary embedded systems with increasingly complex functionalities. Emerging non-volatile memory(NVM) technologies, including the spin-torque transfer magnetic RAM (STT-MRAM), resistive RAM (ReRAM), and phase change memory (PCM), are considered as attractive alternatives in the next generation memory hierarchy. Compared with traditional memory devices, NVM is capable to provide higher density, lower leakage power, as well as non-volatility. However, current NVM devices typically suffer from higher access latency and dynamic power consumption, especially for the write operations due to their inherent nature.In order to fully exploit the superiority of various technologies, hybrid main memory with both DRAM and NVM has been proposed as a promising solution for high performance and energy-efficient computer systems. In general, two architectures have been studied in the literature:(i) using a small and hardware-controlled DRAM as the buffer of the NVM-only main memory space; or (ii) having NVM and DRAM at the same level which constitute the overall main memory address space. In this work, we focus on the latter approach and refer it as the hybrid main memory architecture. The ultimate goal of hybrid main memory is to benefit from both DRAM’s low write latency and NVM’s high density as well as low static power consumption, in order to leverage the overall system performance and/or energy efficiency. To achieve that, most existing studies on hybrid main memory focus on dynamically migrating the physical pages between DRAM and NVM spaces (while keeping their virtual addresses unchanged) via various memory management schemes.However, in a modern processor with caches, when the cache is physically indexed and/or tagged, moving pages between distinct physical memory devices in a hybrid main memory requires substantially high overhead including both memory copy as well as cache update time. Practically, cache management scheme not only determines the total number of cache misses and main memory accesses, but also has large impact on the miss ratio of individual memory blocks. As a result, designing the last-level cache (LLC) management policy is a cost-effective way to control the number of read and write operations on memory blocks located at NVM or DRAM in a hybrid main memory system. On the other hand, the LRU replacement policy is unaware of the significant asymmetry between NVM operations (especially writes) and DRAM operations, leading to non-optimal system designs. Currently, there is only one LLC management scheme HAP for hybrid main memory based on partitioning the cache lines between NVM and DRAM blocks. HAP uses the corresponding read latencies to represent the cost of each cache miss to DRAM or NVM address space. However, as we will show in this paper, given the significantly higher NVM write latency and energy consumption, the write cost of evicting a dirty NVM block from LLC should be taken consideration in the cache management design.In this paper, we propose a write-back aware shared LLC replacement scheme WBAR for high performance and energy efficient hybrid main memory architecture. In general, we design WBAR as a variant of LRU, which is light-weighted and easy to implement. Instead of inserting or promoting the latest visited cache block to the MRU (top priority) position as in LRU, WBAR places a cache block at distinct positions in a cache set according to the potential cost if the cache block is evicted from the cache before it gets reused. Experimental results show that our proposed framework leads to better performance and energy saving compared with the state-of-the-art cache management scheme for hybrid main memory architecture.