Design And Implementation For Communication Channel Equalizer

In the modern digital communication, intersymbol Interference and channel interference by the limited bandwidth and multipath propagation are the most important factors which affect the quality of communication. In order to reduce the interference, blind equalization techniques need to be introduced to the receiver. The blind equalizer can eliminate the intersymbol interference not require a priori information but only through the statistical characteristics of the received signal, and therefore it has been widely used in the field of communication in recent years. Therefore, the design and implementation of efficient channel blind equalizer has some great practical significance for commercial applications and research learning.The application and development of blind equalization technology at home and abroad are introduced in this paper, a multi-modulus blind equalization algorithm based on shuffled frog leaping algorithm is proposed. Its convergence rate is fast, the steady-state error (MSE) is smaller, and it has better equalization performance than the traditional multi-modulus blind equalization algorithm. Then the paper analyzes the characteristics of FPGA and DSP collaborative work, and proposes the use of a dual port RAM chip to complete the communication of the hardware architecture between them. The channel blind equalizer which based on FPGA and DSP channel have been designed and implemented. The equalizer has the advantages of FPGA and DSP, which can well accomplish the task of equalizing the specified algorithm. It is very suitable for testing the blind equalization algorithm in the hardware circuit.According to the design purpose and application requirements of channel blind equalizer, the selection of chips is determined, and the main chips are introduced. Then, the design scheme of blind equalizer based on FPGA and DSP is introduced in detail, which from the system architecture, logical structure, and each function modules and so on. The logic design based on FPGA is introduced, which including the design of the SDRAM controller, the interface design of the dual port RAM on the FPGA side, the design of the D/A converter controller, and the simulation results of each module are given. Subsequently, this paper introduces the blind equalization algorithm based on DSP, as well as the DSP on the dual port RAM read and write operation.In the end, the paper describes the test procedure and the test flow of equalizer equalization performance, and gives the experimental results. The result shows that the equalizer can achieve the equalization of the received signal, and it has good effect. The main advantages of the equalizer are:scalability, portability, real-time. The circuit and hardware system of the independent research design has a lot of function expansion space, it is easy to transplant and replace the blind equalization algorithm, and ensure the realization of the equalizer in real time.