Study And Design Of Class D Audio Power Amplifier

With the audio power amplifier applications scenarios expanding from the fixed electronic equipments without the dimensional-limit and power-limit to the battery-powered mobile devices such as cell phones, laptops, MP3 players; it makes more requirements on the audio amplifiers. Class D amplifier with its high efficiency, small size and improving fidelity gradually replaces class AB amplifier and becomes mainstream products in audio power amplifiers. This thesis aims to design a class D amplifier that can meet market demands.First this thesis shows the conventional amplifiers’ disadvantage about efficiency. Next it analyzes the theories of the class d amplifier, such as its operating principle, non-ideal factors which affect the efficiency, the modulation technologies, the output structure and the low-pass filter which restores the modulation signal. Based on the above theories this thesis proposes a class D power amplifier based on the Δ-Σ modulation technology and the half-bridge output structure.The entire system compose of an integrator, several level shifter circuits and logic control circuits, a dead-time setting circuit, a double-ends over-current detection circuit and so on. One internal high-gain operational amplifier and several external components compose a second-order integrator to implement second-order Δ-Σ modulation; the noise shaping technology ensures low distortion. The programmable dead-time setting circuit can keep the balance between safety and fidelity of the systems. The double-ends over-current detection circuit as a representative of the protection circuits tests the system working conditions, it sends a fault signal in the event of overcurrent. The class D amplifier is generally in the form of double-ends driving which requires a double power supply, so the fault signals sended by the protection circuits are multi-potentials. The logic-control module uniformly processses the multi-potentials fault signals and sends the control signals to shutdown the system. The system restarts after trouble shooting.In the core section of the thesis analyzes the system performance parameters. As follow it proposes the sub-modules structures and analysis the operating principles as well as the key design parameters of the sub-modules.The chip is based on 0.8μm BCD process. The candence software as a simulation tool is used to complete the sub-modules design as also as the system. The final simulation results show the performances of the system meet the original design requirements.