The Design Of High Speed 8b/10b Coding And Decoding Circuit Based On FPGA

With the development of computer peripherals, high-speed serial transmission interfaces are widely used in the communication between computers and Peripheral equipments. And 8b/10B encoding and decoding circuit in serial link is not only ensures the data stream DC balance for the transmission of the serial interface circuit, but also avoids the data loss caused by transmission interface terminal clock drift or synchronous loss in receiving end.With combined advantages of look-up table method and logic combinations, the design work of 8B/10B encoding and decoding circuit is completed in USB3.0 physical layer and meets requirements of USB3.0 for high clock frequency of the codec circuit in this paper, through the design method of increasing the bit width of the data processing so as to reduce the clock frequency of the codec circuit.The specific steps are as followings:1) First of all, the paper introduces the FPGA in detail, including its internal resources, the development process and the design techniques respectively.2) Secondly, the paper analyzes the 8B/10B encoding and decoding specification in detail. It describes the encoding and decoding mapping relations of 5B/6B and 3B/4B two module, the disparity of data flow and the run disparity of the module as well as the violation handling of error code.3) Further, the modular design of the coding and decoding circuit is performed. A balanced detection control output module is a key point in the coding circuit, for which it makes the polarity of data flow output alternately and ensures that the output data flow has direct current balance. In decoding circuit, a violation detection module erroneously detects the input data stream and deals with errors produced in the process of coding circuits or transmission.4) Finally, the design of high-speed 8B/10B encoding decoding circuit is simulated and verified via experiments. The experimental results verify the correctness of the encoding and decoding circuit and meet the design requirements that the circuit works at the frequency of 500MHz.