The Research And Design Of Low Spur Low Jitter Phase Locked Loop In CMOS Process

In recent years, with the rapid development of communication, computation, consumer electronics, the amount of data, need to be generated, transmitted and processed, has been increasing significantly. Therefore, the challenge of designing high-speed IO interface circuit is also increasing. Usually, in the high-speed electrical link system, phase locked loops (PLLs) are used to act as transmitting clock. In order to ensure the high speed data transmitted correctly, high frequency low jitter and low spurs PLLs are needed. This thesis research how to implement low spurs and low jitter for integer-N PLLs and fractional-N PLLs.For a high performance PLL, the design of voltage control oscillator (VCO) is very important, which phase noise and power are the most concerned. In this work, a low phase noise and low power VCO is proposed:the self-switch biasing technique and de-coupled capacitor are used to reduce the flicker noise of tail current, and the body biasing technique is used to reduce the minimum supply voltage. To verify the presented ideas, a 2.396 GHz VCO has been simulated in a 180 nm CMOS process. The simulation results show that the phase noise can be reduced to -71.94dBc/Hz at 10 kHz offset, and the supply voltage can be reduced to 0.5 V.For the 10 Gbps SerDes application, a multi-phases and multi-frequency output PLL is designed, which uses QVCO to generate 4 equal phase space 5.15625 GHz clocks, which go through divided-by-2 divider and then differential buffer,8 equal phase space 2.578125 GHz clocks can be achieved. Besides, a feedback charge pump (CP) is used to achieve low reference spurs. The PLL has been implemented in a 40 nm CMOS process. Design consideration and simulation results have also been presented.To achieve low jitter low spurs PLLs, a 5.15625 GHz sub-sampling phase-locked loop (SSPLL) is designed, which uses QVCO to generate 4 equal phase space clocks. The CP spur is minimized by using differential buffer and complementary switch pairs. The VCO sampling spur effect is also minimized by using dummy samplers and CML isolation buffers. In addition to low reference spur, the SSPLL also achieves low RMS output jitter because the divider noise is eliminated and the SSPD and CP noise is not multiplied by N2. The SSPLL is implemented in a 40 nm CMOS process. Design consideration and simulation results have also been presented.In fractional-N PLLs, due to  modulator, the loop nonlinear transfer characteristic will cause quantization noise folding and result in an increased in-band noise. A pulsed offset current linearization technique has been proposed by simply adding a replica PFD/CP. It can eliminate noise folding, while it will not deteriorate reference spurs. The effectiveness of the proposed linearization technique has been verified by theoretical analysis and simulation.