Research And Realization Of The Decoding Technology On Turbo Product Code

Channel coding technology is one of the key technologies in digital communication system. It has become one of the most important branches of modern communication subject. Researchers have been trying to find a coding scheme, which performs similar to Shannon Limit, and with low complexity of decoding. In 1994, Pyndiah et al proposed Turbo Product Code (TPC), it has inherited the advantages of Turbo Code which performs close to Shannon limit, and has a lower decoding complexity than Turbo Codes as well. In recent years, TPC has gradually become a hot topic in the field of channel coding.This thesis describes the structure as well as the encoding and decoding principles of TPC, and then focuses on the decoding algorithm of both soft and hard decision. Soft-decision iterative decoding algorithm which based on Chase algorithm has been also improved in this study. The improved decoding algorithm and the original algorithm have been verified by simulation in Matlab2008. We also do some comparative analysis to the results of the simulation, which shows the merits and demerits of each decoding algorithm. Simulation results indicate that the modified decoding algorithm has been improved in performance than the original decoding algorithm. Meanwhile the various factors affecting the performance of Turbo Product Codes are simulated, and the simulation results was compared and analyzed.On the basis of algorithm simulation, the FPGA designing program of TPC simulation is presented finally. The author elaborates the overall design, the implementation process and the realization of each module. The sub-code code-type adopted the truncated (54,47)BCH code that plus a parity bit. When we design the decoder by FPGA, we divide them into several sub modules according to the top-to-down design idea, and that makes then design more flexible. We regard the spartan-3/xc3s4000-4FG676 chip of Xilinx Company as the target chip. By using Verilog Hardware Description Language, the design and synthesis of the TPC decoder have been completed in ISE9.2. Then, time sequence simulation has been implemented in Modelsim10.0C. Simulation results show that the decoding algorithm designed by FPGA is consistent with the performance of Matlab simulation results.In the end of this thesis, the author concludes the results of this study, points out the areas to be improved, and puts forward the work plan of next step.