Research On The Technologies For Host Interface Controller Of NAND Flash

With the widely used of NAND Flash memory in a variety of digital products and mobile handsets, and the increment of requirements asked by users for storage capacity and performance, the memory controller technology has become a critical impact on performance. e MMC(embedded Multimedia Card) chip is the most popular embedded memory for now, which developed specifically for smart phones and other portable devices to fully meet the their needs. e MMC chip should follow e MMC protocol. The protocol is an international unified communication specification established by the JEDEC association.This paper describes e MMC 4.5 protocol contained structure and function under current background. A controller faced to host based on e MMC protocol was designed by a top-down design methodology. The controller can be realized to process commands and data according to the protocol. The controller is composed of a command control module and a data control module. Each of them consists of several sub-modules. These modules are implemented by Verilog HDL RTL code. The design of the controller used some techniques such as logic share, metastable synchronization, to optimize the performance.In the first stage of verification, the RTL code was fully verified by functional simulation. Then analysis of operation of command and data was going during the simulation. Later the controller was verified with FPGA(Field-Programmable Gate Array) and a logic analyzer used to collect and observe waveforms. Finally, the controller was proved workable.