Design And Verification For A Kind Of High Speed MCU Compatible With MCS-51 Instruction Set

Since Intel introduced 8051 microcontroller in 1980, microcontrolls,compatible with MCS-51 instructions set, gradually become the mainstream in the eight bit mcu market. During past ten years, lots of major chip manufacturers were launching their own microcontrollers,which are compatible with MCS-51 instructions set, with the MCS-51 instructions set patents expiring.Currently, the execution efficiency of microcontrols on the market,which are compatible with MCS-51 instructions set,is usually lower than 20 MIPS,which severely restricts applications of these microcontrollers in high-speed data processing. In order to improve the efficiency of MCS-51 instructions set, HIT Shenzhen Graduate School So C Research Center, using multi-cycle technology and pipelining technology,design a microcontroller c8051,compatible with MCS-51 instruct ions set,whose instruction execution efficiency can up to 36 MIPS.In this thesis, I use two true dual-port eight ROM and two single-port eight ROM to construct c8051 program memory structure. Using such a program memory structure,The c8051 IP can fetch all the aperands and operands in one clock cycle for all kinds of instructions,which makes c8051 IP can execute instruction in five stage pipelined line,which are similar to the MIPS instruction, and that greatly improves the efficiency of executing instructions c8051 IP. The storage instructure of c8051 IP is Harvard architecture,which means programs and data are stored in the program memory and data memory separately.Its data memory consists of three parts:working registers,on-chip RAM and Special Function Registers,the address for which are encoded consistently. c8051 IP support interrupt operation.Before the microcontroller interrupt service routine, c8051 IP use data path and control path of LCALL instruction to achieve the pushing stack of PC operation. In order to facilitate communication with the outside chip, in this thesis I designed UART, SPI and I2 C interfaces for the c8051 IP. These UART, SPI and I2 C module support interrupt queries and software polling.In order to verify the function of the c8051 IP, the last part of the thesis completed the MCU core single instruction tests and benchmark tests. In the MCU single instruction test part, I use System Verilog port packaging MCU kernel, and then inserting System Verilog assertions to the test module to build automated test platform for the single-instruction testing. In the benchmark test part,with the help of perl script, the Keil compiler and Ncsim, the thesis build platform for benchmark testing.