Monte Carlo Simulation Of Mixed Spin Diamond Chain Ising Model Based On FPGA

By virtue of its simple structure and rich content, Ising model is widely used in statistical physics. The research of the magnetic properties of the mixed-spin diamond chain Ising model has guiding significance for the experimental and applied research of a number of compound materials which have effect of spin resistance. Numerical simulation of the Ising model requires a lot of computational work, due to the limitations of traditional computer data width, the calculation time required for a relatively long; FPGA with its significant advantages in terms of parallel computing that can greatly save the simulation time.Firstly, through the discussion of Monte Carlo method on the model simulations the theory of one-dimensional diamond chain Ising model has been introduced in this paper, summed up the implementation method of model design of hardware, which makes the model state can be updated in parallel.Secondly, in this paper, the design based on FPGA platform, Verilog hardware description language were used to design and implement a one-dimensional diamond chain Ising model whose spin state update according to the energy change, in the design process, because the number of cell model is large, occupying too many resources, in order to save resources by using the design method of series parallel combination, not only makes the model update speed ascension, but also saves logic resources.Thirdly, in order to make the data analysis of Ising model convenience, a system for the model has been designed in this paper. Data generation module, storage module, and data processing module and control module were included in this system. The core of the system is the data generating module, namely Ising model function simulation module. All the current state of spins will be stored in the memory module at each clock. Data from the storage module will be read and processed by processing module; and finally the data will be transmitted to the computer through URAT and displayed on LED screen. All above actions are operated by the control module that can enable and disenable the other modules.Finally, this paper described the functional implementation on FPGA and the overall scheme of the data transmission between modules which were carefully designed and tested, we also compared our design with traditional computer simulation, that state Ising model in the FPGA update speed is comparable to more than 100 personal computers.