Design Optimization And Exprimental Investigation Of High Voltage Silicon Carbide VDMOS Devices

Silicon carbide vertical double-diffusion metal-oxide-semiconductor field-effect transistor(SiC VDMOSFET, known as SiC VDMOS) is the power device of the next generation fabricated on the silicon carbide, one of the wide band-gap semiconductor materials. The large band-gap, high critical electric field, high thermal conductivity and high electron saturated drift velocity of SiC bring it a very promising application prospect in the power electronics field requiring high power, high temperature and high frequency. For the present, SiC power devices have been maturely commercialized overseas. However, the study in this field at home is still at a primary R&D stage. Based on the practical conditions of domestic research institutes, this thesis focuses on the static characteristics, optimizes the device structures and investigates the crucial processes of high voltage 4H-SiC VDMOS devices in the hope of offering primary references to the domestic study.Through computer numerical simulations, the effects of parameters of the high voltage 4H-SiC VDMOS cell structures on the conduction and blocking characteristics are investigated, whose parameters include the JFET region width, channel length, gate oxide thickness and the Pbase doping profile. Following the optimization of the cell structure, both field limiting ring(FLR) and junction termination extension(JTE) junction termination structure are designed. One the one hand, a linearly graded field limiting ring(LG-FLR) termination is proposed based on the conventional FLR structure, which modulates the effective lateral doping concentration along the termination by applying graded increasing ring widths, resulting in a smooth distribution of electric field and even potential dropping with a termination efficiency of 89% and smaller termination area. On the other hand, the etched JTE termination is investigated, which is supposed to increase the process tolerance. Due to the premature breakdown caused by the high dose of JTE termination, which results from the simultaneous implantation with Pbase regions, thus etching is employed to reduce the effective dose of JTE, realizing a termination efficiency higher than that of FLR structures.Due to the process distinctivenesses of fabricating high voltage 4H-SiC VDMOS devices, this thesis investigates into the high temperature ion implantation and channel self-aligned process. The secondary ion mass spectroscopy results demonstrate that the design of implantation energy and dose derived from the SRIM/TRIM simulator manages to form the desired doping profile of the Pbase, N+ source and P+ regions. Besides, to realize submicro channels without lithography errors, a channel self-aligned process without thermal oxidation is investigated, which develops self-aligned channels with sidewalls formed by etching deposited SiO2. Finally, the device layout is designed according to the optimized high voltage 4H-SiC VDMOS structures, following with tapeout experiments and testing analyses.