The Optimization Of Coprocessor In Heterogeneous Multi-core System

With the progress of integrated circuit and the demand for higher performance chip, the traditional method which is aimed to improve frequency and performance through constantly miniaturizing the route already can’t meet the design requirements. So the multi-processor System-On-Chip (MPSOC) technology arises at the historic moment. Compared with the single processor system, multi-core system has the advantage of low power consumption, high degree of parallelism. The appearance of multi-core processors will make the development of micro-processor change from seeking a higher frequency of a single core to seeking more processor cores. The large hierarchical array of cores will become the development direction of multi-core system. The research object of this paper is a kind of SOC system based on NOC network which has small cores and large array.In the multi-core system, the floating-point coprocessor can improve the efficiency of the special operation, provide greater space for main processor and give enough freedom to the software programming at the same time. Besides, it can simplify the multi-core programming, control subtasks better, be conducive to cooperation between cores and improve the overall performance of the multi-core system. The main work is as follows:Firstly, this thesis analyses the requirements of the coprocessor in the heterogeneous multi-core system and shortages of the existing coprocessor, and then looks for ways to improve.Secondly, by studying the out-of-order emission computer system, this thesis presents an out-of-order launch plan which can be applied to the high density calculation, batch operations and spurious operations.Finally, based on the optimization scheme, the RTL design was completed. The performance of the system was analyzed and assessed through the experiment, proved that the performance advantage and practicability of the optimization design.