Design Of All-digital Phase Locked-loop Based On Linear Enhanced TDC

Phase-locked loop as internal high-speed clock provider, is essential in modern circuit, almost all the digital circuit will use it. The performance and area of conventional PLL is constrainted by the analog circuit it contains. Digital integrated circuit, which has advantages of strong anti-interference ability, good portability, small size and low power consumption, make ADPLL widely used.TDC is an important component of ADPLL, its resolution determines the close degree of the PLL output signal frequency and the reference frequency, and its dynamic range determines the capture range and locking time. This paper uses the TDC which has counter and delay chain mixed structure, this structure can solve the contradiction between resolution and dynamic range of the time to digital converter. For the delay chain, this paper presents a linear enhancement algorithm, which greatly improved the integral nonlinearity of TDC.This paper first introduces the history and significance of the study of phase locked loop, compares the advantages and disadvantages of the traditional PLL and ADPLL. Then, this paper expounds the principle, structure and mathematical model of PLL. The working principle of all digital phase-locked loop,and the structure and mathematical model of each sub-module is described in detail, the sub-modules includes phase frequency detector, time to digital converter, digital loop filter and digitally controlled oscillator. The principle and the design implement of linear enhancement TDC will be emphasized. At the end of this paper, the design process and the simulation results of each module of ADPLL is described detailly.In this paper, the ADPLL is designed in 0.18μm CMOS process. The designs and simulations of all the modules have been completed. The output frequency of the ADPLL can be locked properly. The locking time is about 2μs, and the output frequency is 250 MHz, peak-peak jitter is 76 ps.