Study Of Novel Structure And Threshold Voltage Model For Nanometre CMOS Devices

With the scaling of CMOS(Complementary Metal-Oxide-Semiconductor) devices, traditional MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor) presents more and more severe SCEs(Short Channel Effects). A lot of new structures have been proposed to replace traditional MOSFET at the deep submicron node, in order to suppress SCEs and improve the performance. Among them, DMG(Dual Material Gate) and DI(Dual Insulator) are two new structures that can both suppress SCEs and improve carrier transport efficiency.In this paper, a new structure called DMG-Bulk-FinFET is proposed by incorporating DMG structure into bulk-FinFET(bulk-Fin Field-Effect Transistor). By using three-dimensional(3-D) simulator DAVINCI, the performances of DMG-Bulk-FinFET and traditional bulk-FinFET are compared. It is proved that the new structure can suppress DIBL(Drain Induced Barrier Lowering) effect and increase current and transconductance. In addition, the influences of DMG structure’s most important parameters: gate length ratio and workfunction difference are analyzed. As a result, the optimal parameters of DMG structure used on bulk-FinFET are suggested.A new analytical model of surface potential of DI-DG(Dual Insulator Double Gate) MOSFET is derived by using a new method. And also, analytical models of threshold voltage for both common DI-DG MOSFET and long-channel DI-DG MOSFET are calculated. By comparing the simulation results from 2-D simulator MEDICI and model results, models of surface potential and threshold voltage both show a good match. The different influences on device performances by changing the structure parameters are also compared and analyzed.