Research And Design Of 2.4GHz CMOS All Digital Phase-locked Loop

With the development of the deep-submicron CMOS technology, the reduction of the size of process makes the analog circuit design become more complex. It becomes a trend to use digital design instead of analog design. Phase-locked loop(PLL) as the clock generation circuit is a key module in RF communication system, wherein all digital PLL(ADPLL) with good integration, portability and programmability which can achieve better phase noise performance and other advantages has been widely researched and developed.In this paper, the work focuses on the research and design of a 2.4GHz CMOS ADPLL, which mainly includes: 1) The performance of ADPLL is analyzed, the principle and structure of type-I and type-II ADPLL is given and the influence of the loop parameters on the loop characteristics and stabilities is analyzed. 2) A complementary comparator for time-to-digital converter(TDC) is proposed. Based on the traditional structure, the complementary comparator is stacked on it. The new comparator can eliminate the burr of the output waveform, increase the comparator working speed, reduce the input offset voltage, and improve the precision of the comparator. 3) A new reconfigurable digital loop filter(DLF) is proposed. The DLF parameters KP and KI are made off chip, By manually adjusting the internal parameters of the loop off chip, the bandwidth, the open and closed loop response, and the amplitude response can be changed together. Eventually the ADPLL can conveniently reach the lock state by hand. 4) A high precision digitally controlled oscillator(DCO) is analyzed and designed. This DCO uses CMOS cross-coupled LC oscillator and is comprised of three capacitor arrays: coarse,medium and fine tuning bank, and ΔΣ modulator. The coarse tuning bank uses MIM capacitors, the medium and fine tuning bank use two pairs of reversed-connected PMOS as MOS capacitors. The gain of the DCO is about 300 kHz. With the use of ΔΣ modulator, the resolution of DCO can be reached up to about 5kHz.This work is designed under SMIC 0.18μm CMOS technology, using the top-down method to accomplish a 2.4GHz ADPLL. It includes five important modules: TDC, DCO, DLF, ΔΣ modulator and divider. The simulation results show that: under the 1.8V supply, the precision of TDC is 16.6ps, the frequency range is 2.33~2.55 GHz, the phase noise is-120.7dBc/Hz@1MHz, the rms jitter is 8.75 ps, the peak-to-peak jitter is 54.07 ps, the total power consumption is 32.6mW, the locking time is about 20μs, and the chip area is 1.32mm2, which meet the requirements of the expected design.