The Research And Implementation Of An OTN Performance Testing System Based On CPU-GPU Heterogeneous Computing Platform

Ever since the beginning of the cloud computing era, higher requirements of network flexibility and programmability have been put forward for the optical transport network(OTN). OTN architectures that adopt computer application technology has become one of the mainstream researches on OTN.The content of the research in this thesis is provided by Flex-OTN simulation platform, a project by Huawei Technology Co.Ltd. Functionnally, the system is consisted of two subsystems, implementing the mapping and de-mapping procedure of client signal separately, achieving 10Gbit/s throughput in each subsystem and providing system performance testing interface for runtime status monitoring.The mapping subsystem implements the mapping procedure of client signal. Its functions include reception of ethernet frames, mapping of ethernet frames into GFP(generic framing procedure) frames, mapping of GFP frames into OTU(optical channel transport unit) frames and transmission of OTU frames.The de-mapping subsystem implements the de-mapping procedure of client signal. What it does includes reception of OTN frames, de-mapping of OTU frames into GFP frames, de-mapping of GFP frames into ethernet frames and transmission of ethernet frames.In order to improve the throughput of the system, this thesis makes invocations in a number of aspects.In system architecture, with the technology of CPU-GPU heterogeneous computing, parallel the system’s processing flow between different computing devices,as the central processing unit is responsible for the overall control and the graphics processing unit is responsible for data processing. Design system architecture to realize efficient collaboration between system hardware and software.In task scheduling, adopt the TSC(time stamp counter) as clock source and employ the polling strategy to overcome the equipment’s lack of interruptability. Design the timing framework and put forward the concept of critical point in timing cycle, solving the random interruptions’ effects on timing accuracy.In data transmission, by modifying the operating system’s kernel page table, remap memory cache into kernel address space, avoiding the unnecessary memory copy operation between kernel and user address space.In data processing, adopt multi-core parallel and GPU parallel these two parallel design patterns. Design the multi-core GFP processing procedure and the GPU parallel algorithms of BIP8, FEC and scrambling. Optimize operation performance to achieve the throughput requirements.