Research On Aging Model In High-k Gate Dielectric CMOS Integrated Circuit

With the advances in integrated circuit technology, the aggressive scaling down technology has largely improved the integration level and function of integrated circuit. However, it also has brought more challenges to the reliability of circuits. One of these challenges is circuit aging on which researchers have been paying more and more attention. Nowdays, main research work concerning to circuit aging include two aspects, which are aging modeling and aging optimization for the silicon-based MOS transistors and integrated circuits. When circuits are processed using down to 45nm technology, the shrinking silicon feature size brings in high-k gate dielectric using in order to alleviate the increasingly serious phenomenon of gate leakage current. This dissertation focuses on modeling the circuit aging effects in high-k gate dielectric MOS transistors.Introducing high-k gate dielectric into the high-k/metal gate MOS transistor will significantly exacerbate the NMOS transistor aging effects called positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). A hybrid aging delay model is proposed in this dissertation, which comprises both PBTI and TDDB effect through analyzing the relationship between aging propagation delay and inherent delay of the gate. Experimental results by HSPICE under 45nm,32nm, 22nm and 16nm technologies show that the maximum error of the proposed model to the actual value is less than 2.5%, the average error being about 1.5%. It is also demonstrated in this dissertation with the experiments on an inverter chain that the delay caused by jointly considering the effect of PBTI and TDDB is more accurate than the simply cumulating result of the delay caused by PBTI and TDDB respectively. The proposed model provides a relatively simple prediction algorithm for the circuit aging delay of the high-k/metal gate MOS transistor.By linear analysis and data fitting, a new PBTI aging model of high-k material gate MOS transistor is also established in this dissertation based on trapping/de-trapping mechanism. The experimental results show that within eight to twelve years of predicted time, the average errors of the proposed model with simulation results by HSPICE are from 2% to 4.5%, thus verifying the correctness of the model. Under the same circuit reliability, compared with the timing margin setting experimental results of the previous aging delay model using three different critical paths, timing margin needed by the proposed model is significantly reduced when the time index n is 0.16 and 0.25, Therefore, this dissertation provides a better reference to setting the circuit timing margin when design.