FPGA-Based Network-on-Chip Simulation And Distributed Timing Modeling

With the advent of multi-core era, more and more cores can be integrated on a single chip. Communication between these cores has become a crucial factor to performance in multi-core/manycore systems. Traditional bus-based interconnection is hard to supply the communication demand because of low-bandwidth and poor scalability. Therefore, Network-on-Chip (NoC) is proposed as a substitute by architects. It separates On-chip communication from IP Cores, then multiplexes and parallels communication flows over these node interconnects, so the problem of bandwidth and scalability can be well solved. NoC has been the hotspot in architecture research. However, in the works of NoC modeling, traditional software NoC simulators are intolerable in simulation speed and the newer hardware-based solution is poor in scalability. There are still no satisfactory ones. Aiming at the problems occurred in previous researches of NoC simulators, this work starts from NoC timing modeling methods and ultimately designs a fast, extensible and cycle-accurate NoC simulator.The major research contributions of this dissertation include:(1) We summarized and analyzed existed FPGA-based NoC timing modeling methods and borrowed the advantages of them. In addition, aiming at the drawbacks, we proposed a hardware-friendly distributed timing control scheme. This scheme uses implicit synchronization methods and replaces centralized controller with intra-node counters and inter-node buffer queues, so each node can solely deal with the tasks of synchronization and counting.(2) We designed and implemented a fast, extensible and cycle-accurate NoC hardware simulation system with distributed timing control scheme. This system keeps parameterization and virtualization in mind, so it is convenient for users to simulate different various NoCs and make tradeoffs.(3) The simulation system is compared with representative NoC simulators to quantitively evaluate its correctness, scalability and performance. Experimental results demonstrate that this simulator can achieve similar accuracy to widely-used software ones and gain200-fold speedup. Compared with a recent hardware implementation, it solves the scalability problem and accelerates simulation by21%at most. The NoC distributed timing control scheme targeted at FPGA is inspired from the simulation of synchronization systems. Therefore, it is universal and can be a reference to other FPGA-based architectural modeling of synchronization systems.